In sensing a dynamic random access memory (DRAM) storage cell, it is necessary to generate a reference voltage between sense levels of “1” and “0” data types for differential sensing. More specifically, a level of the reference voltage VREF may be set to balance a signal margin between the “1” and “0” data types. For example, reference cells may be used where “0” and “1” levels are mixed, and a half-level is used to sense a DRAM data type. However, this scheme may lack an effective, predictable signal margin test. In addition, since the “1” data type may require an additional leakage margin for retention, the half-level used to sense the DRAM data type may not be optimal.
In another example, a linear voltage divider may be used to generate a VREF level equal to a fraction of a bitline power supply, and the fractional VREF level may be used to precharge reference cell capacitors. During a read operation of a DRAM, the VREF level is coupled to reference bitlines through reference cell access transistors. The VREF level may be scaled with a power supply voltage of e.g., 1 to 1.8 volts (V) in embedded DRAM (eDRAM) designs.
However, silicon on insulator (SOI) eDRAM may be designed with a floating body cell device which is susceptible to increased subthreshold leakage at high supply voltages due to a charge-up of the floating body cell device. More specifically, this increased subthreshold leakage may be due to junction leakage effects in the floating body cell device between drain and body terminals and between source and body terminals. For example, when a bitline is high (e.g., includes a write-back to another address), junction leakages may raise a body voltage in the floating body cell device. This lowers a threshold voltage of the floating body cell device, and increases leakage in the floating body cell device.
In addition, as junction and subthreshold leakages increase with a higher power supply voltage, a margin between the reference voltage and a voltage of a “0” data type may be degraded. A voltage level of a “1” data type is limited by a cell wordline level, so while the higher power supply voltage increases the “0” margin, the higher power supply voltage does not add to a margin between the reference voltage and the voltage of the “1” data type. Furthermore, scaling of the reference voltage in proportion to the power supply voltage may reduce the “1” margin as the power supply voltage increases, even though the scaling may improve the “0” margin.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.